Search - vhdl core

[VHDL-FPGA-Verilog] DUC

Description: 数字上变频DUC是与数字下变频ddc相对应的工作.目前实现方式主要有:专用芯片,通用DSP和FPGA实现三种.本程序即给出了XILINX公司的Digital Up Converter核心程序(IP CORE)以及响应的使用说明,对于从事雷达,无线通信的工程人员和研究者有很大用处.-DUC is a digital up-conversion and digital down conversion that corresponds to the work of ddc. Realize the current approach are: ASIC, DSP and FPGA generic realize three. This procedure is given that the company XILINX core Digital Up Converter program (IP CORE) and to respond to instructions, for radar, wireless communications, engineers and researchers have great usefulness.
Platform: | Size: 305152 | Author: 周严 | Hits:

[ActiveX/DCOM/ATL] CORDIC_ip

Description: cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v r : Cordic Mode. r = Rotation, v = Vectoring 32 : Precision of the individual vector components. 16 : Precision of the angle. 12 : Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
Platform: | Size: 457728 | Author: abcoabco | Hits:

[Other] sd_IP

Description: SD card controller can just read data using 1 bit SD mode. I have written this core for NIOS2 CPU, Cyclone, but I think it can works with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core. Good luck-SD card controller can just read data using 1 bit SD mode.I have written this core for NIOS2 CPU, Cyclone, but I think it can workswith other FPGA or CPLD. Better case for this core is SD clock = 20 MHz andCPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.Good luck
Platform: | Size: 8192 | Author: tuya | Hits:

[VHDL-FPGA-Verilog] 4

Description: 控制模块是频率计的核心所在,具有如下所述功能：对输入数据判断并输出档位信号； ——10KHZ最高位为1010，换高档，最低位为0000，小数点不亮，表无信号； ——100KHZ最高位为1010，换高档，最高位为0000，换低档测试； ——1MHZ、10MHZ同100KHZ测试档。针对不同的档位输出不同的时基信号； ——100ms时基信号，用于10KHZ档位测量 ——10ms时基信号，用于100KHZ档位测量 ——1ms时基信号，用于1MHZ档位测量 ——0.1ms时基信号，用于10MHZ档位测量 -Control module is the core of Cymometer with features as described below: The input data to determine and output stall signals - 10KHZ highest for 1010, for high-grade, the lowest for 0000, the decimal point does not shine, table-free signal ---100KHZ highest for 1010, for high-grade, the highest for 0000, for low-grade tests - 1MHZ, 10MHZ with 100KHz test file. Stalls for different output signals of different time-base - 100ms time base signal for the measurement of 10KHz stalls- 10ms time base signal for the measurement of 100KHz stalls- 1ms time base signal for 1MHz stalls Measurement- 0.1ms time base signal for the measurement of 10MHz stalls
Platform: | Size: 2048 | Author: 张伯伦 | Hits:

[VHDL-FPGA-Verilog] uart

Description: M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。-M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx
Platform: | Size: 18432 | Author: lc | Hits:

[Com Port] uart

Description: 一个基于硬件描述语言的uart核该软核灵巧方便，占用资源小波特率可调-A hardware description language based on the UART core of the soft-core smart convenient, small footprint adjustable baud rate
Platform: | Size: 3072 | Author: xu | Hits:

[VHDL-FPGA-Verilog] dds

Description: DDs直接数字频率合成器的源代码，其中包括采用IP核和普通两种方式-DDS Direct Digital Synthesizer source code, including the use of IP core and the general two ways
Platform: | Size: 1378304 | Author: 谭儆轩 | Hits:

[VHDL-FPGA-Verilog] ISP

Description: ISP的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-ISP of the IP core, can be used to download, unzip to the specified directory can be a light inside the read me.
Platform: | Size: 4096 | Author: 王鹏 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera

Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能：（1）在液晶屏上显示时间、日期、状态提示；（2）利用4个按键对时间（时分秒）、日期（年月日）进行设置；（3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock
Platform: | Size: 6460416 | Author: Emma | Hits:

[Software Engineering] ps2_ipcore_design

Description: 电子测量技术 ELECTR0NIC MEASI瓜EMENT TECHN0L0GY 第29卷第3期 2006年6月 PS／2设备接口IP核设计王豪黄启俊常胜 (武汉大学物理学院微电子与固体电子学实验室武汉430072) 摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的设计思想，并在FPGA上进行验证。结果表明此核功能正确，可以方便地在SOPC系统中复用。-Electronic Measurement Technology ELECTR0NIC MEASI melon EMENT TECHN0L0GY Vol 29 No. 3 June 2006 PS/2 device interface IP core design黄启俊Changsheng WANG Hao (School of Physics, Wuhan University Microelectronics and Solid State Electronics Laboratory, Wuhan 430072) Abstract: Verilog hardware description language to achieve a PS/2 device interface of II) of nuclear design, described in detail II) the structure of nuclear division and the module
Platform: | Size: 126976 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: RISC CPU IP CORE 可以用于直接的工程开发应用有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure
Platform: | Size: 574464 | Author: 毋杰 | Hits:

[Other] mpdma.tar

Description: DMA VHDL 设计IP核经常遇到大数据交换要用DMA，本IP核来自开源组织，免费开源版-DMA VHDL design IP core often encountered in large data exchange to use DMA, the IP core from the open-source organizations, free open source version
Platform: | Size: 93184 | Author: | Hits:

[Other] mdct.tar

Description: 图像编码如H263 264 AVS等编码都要用DCT变换，DCT变换IP核很有用-Image coding, such as H263 264 AVS must be used, such as DCT transform coding, DCT transform IP core very useful
Platform: | Size: 1770496 | Author: | Hits:

[VHDL-FPGA-Verilog] logvhdl

Description: altera的关于对数计算的IP core。-altera calculated on the logarithm of the IP core.
Platform: | Size: 116736 | Author: max | Hits:

[MPI] butterfly

Description: 附件代码实现了基4FFT的碟形单元运算，是FFT算法的核心部分，并且此碟形单元运算是基于浮点运算的-Annex code base of the dish 4FFT computing unit is the core of the FFT algorithm, and this dish is based on the computing unit of the floating-point operations
Platform: | Size: 4096 | Author: 钟毓秀 | Hits:

[assembly language] 8086

Description: vhdl 8086 core -vhdl 8086 core
Platform: | Size: 1226752 | Author: 姜兆刚 | Hits:

[VHDL-FPGA-Verilog] uart16550.tar

Description: uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
Platform: | Size: 246784 | Author: 姓名 | Hits:

[Firewall-Security] FPGAFirewall

Description: 本系统由服务器软件控制平台和fpga硬件处理系统组成，其中fpga硬件处理系统是整个系统的核心部分。系统管理员通过服务器的软件控制平台可以对fpga硬件处理系统进行即时的配置，fpga硬件处理系统按照系统管理员的配置进行工作，并会在检测到异常情况或者检测到用户敏感的流量或者数据包的时候通知服务器，服务器会向管理员发送通知。管理员可以在服务器软件平台上做进一步的分析处理。-The control system consists of server software platform and FPGA hardware processing system, of which FPGA hardware processing system is the core of the whole system. System administrator through the server software control platform FPGA hardware can perform real-time processing system configuration, fpga hardware processing system in accordance with the system administrator s configuration, and will be detected or the detection of anomalies to the user-sensitive traffic or packet when the notification server, the server will send a notification to the administrator. An administrator can in the server software platform for further analytical processing.
Platform: | Size: 6212608 | Author: 李佳琦 | Hits:

[VHDL-FPGA-Verilog] hgb_pci_host

Description: 内有一PCI 主和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。本PCI_HOST目前支持： 1、对目标PCI_T进行配置； 2、对目标进行单周期读写； 3、可以工作在33MHZ和66MHZ 4、支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
Platform: | Size: 2712576 | Author: | Hits:

[VHDL-FPGA-Verilog] C8051

Description: VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
Platform: | Size: 739328 | Author: | Hits:

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